MT40A512M16LY-062E IT:E

MT40A512M16LY-062E IT:E is a MT40A512M16 DDR4 SDRAM in a 96-pin FBGA package. The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

• VDD = VDDQ = 1.2V ±60mV, VPP = 2.5V, -125mV, +250mV
• On-die, internal, adjustable VREFDQ generation
• 1.2V pseudo open-drain I/O
• Programmable data strobe preambles
• Data strobe preamble training
• Command/address latency (CAL)
• Multipurpose register READ and WRITE capability, write levelling
• Low-power auto self refresh, temperature controlled refresh, fine granularity refresh
• Maximum power saving
• Output driver calibration

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.