MT53E128M32D2FW-046 WT:A

MT53E128M32D2 is a mobile low-power DDR4 SDRAM (LPDDR4). It is a high-speed CMOS, dynamic random-access memory internally configured with either 1 or 2 channels. Each channel is comprised of 16 DQs and 8banks. It uses a 2-tick, single-data-rate (SDR) protocol on the CA bus to reduce the number of input signals in the system. The term "2-tick" means that the command/address is decoded across two transactions, such that half of the command/address is captured with each of two consecutive rising edges of CK. The 6-bit CA bus contains command, address, and bank information. Some commands such as READ, WRITE, MASKED WRITE, and ACTIVATE require two consecutive 2-tick SDR commands to complete the instruction. Read and write accesses to the device are burst-oriented. Accesses start at a selected column address and continue for a programmed number of columns in a programmed sequence.

• Operating voltage is 1.10V VDD2/0.60V or 1.10V VDDQ
• 128 meg x 16 configuration
• 2 die addressing, clock-stop capability, single-ended CK and DQS support
• Cycle time is 468ps, tCK RL = 36/40
• Clock rate is 2133MHz, data rate is 4266Mb/s/pin
• Bidirectional/differential data strobe per byte lane, partial-array self refresh (PASR)
• Programmable READ and WRITE latencies (RL/WL), selectable output drive strength (DS)
• Directed per-bank refresh for concurrent bank operation and ease of command scheduling
• Operating temperature range is -25°C to +85°C
• Package style is 200-ball TFBGA