Product Information
Product Overview
The 74HC107D is a dual negative edge triggered JK Flip-flop featuring individual J and K inputs, clock (CP\) and reset (R\) inputs and complementary Q and Q\ outputs. The reset is an asynchronous active low input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flop. The J and K inputs must be stable one set-up time prior to the high-to-low clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.
- CMOS Input levels
- Complies with JEDEC standard No. 7A
Applications
Industrial, Consumer Electronics, Computers & Computer Peripherals
Warnings
Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.
Technical Specifications
74HC107
-
25mA
SOIC
Negative Edge
2V
74HC
-40°C
-
MSL 1 - Unlimited
JK
78MHz
SOIC
14Pins
Complementary
6V
74107
125°C
-
To Be Advised
Technical Docs (2)
Legislation and Environmental
Country in which last significant manufacturing process was carried outCountry of Origin:Thailand
Country in which last significant manufacturing process was carried out
RoHS
RoHS
Product Compliance Certificate