74HC112PW,118

74HC112PW,118 is a dual negative-edge triggered JK flip-flop. It features individual J and K inputs, clock (n active-low CP) set (n active-low SD) and reset (n- active-low RD) inputs. It also has complementary nQ and n active-low Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. It features ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V).

• CMOS input level
• Asynchronous set and reset
• Specified in compliance with JEDEC standard no. 7A
• Supply voltage range from 2V to 6V
• Input leakage current is ±0.1μA max at (VI=VCC or GND;VCC = 6.0V, 25°C)
• Supply current is 4μA max at (VI=VCC or GND;IO = 0A;VCC = 6.0V, 25°C)
• Input capacitance is 3.5pF typ at (25°C)
• Propagation delay is 55ns typ at (VCC = 2.0V, 25°C)
• Operating temperature range from -40°C to +125°C
• TSSOP16 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.