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Evaluation Kit, HMC7044LP10BE, Dual Loop Clock Jitter Cleaner, 3.3 to 5 V Supply


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EK1HMC7044LP10B   Datasheet
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Product Overview

EK1HMC7044LP10B is an evaluation board to evaluate the HMC7044 dual loop clock jitter cleaner. The HMC7044 meets the requirements of multicarrier GSM and LTE base station designs and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The high performance dual-loop core of the HMC7044 enables the base station designer to attenuate the incoming jitter of a primary system reference clock, such as a CPRI source, with the help of the narrow-band configured first PLL loop, which disciplines an external VCXO and to generate the low phase noise, high frequency clocks with the wider-band second PLL to drive data converter sample clock inputs.

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Analog Devices


Clock & Timing

Clock Jitter Cleaner

Evaluation Board HMC7044LP10BE, USB Interface Board and USB Cable


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Technical Documents (1)

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CAD Models - Notice
CAD Models and drawings are provided to you on a revocable limited licence for your internal use only but remain the property of the manufacturer who retain all intellectual property rights and ownership. They are provided to assist you in decision making and as design guide but are not guaranteed to be error free, accurate or up to date and is not intended to be taken as advice.
Use of these CAD models and other options provided are downloaded and used entirely at your own risk and by continuing you confirm acceptance of the above.

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