74HCT109D,653

74HCT109D,653 is a dual positive edge triggered J active-low K flip-flop featuring individual J and K inputs, clock (CP) inputs, set and reset inputs and complementary Q and active-low Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and active-low K inputs control the state changes of the flip-flops as described in the mode select function table. The J and active-low K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The J active-low K design allows operation as a D-type flip-flop by connecting the J and active-low K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

• Toggle flip-flop or "do nothing" mode
• Wide supply voltage range from 4.5V to 5.5V
• CMOS low power dissipation, high noise immunity
• TTL input level, latch-up performance exceeds 100mA per JESD 78 Class II Level B
• It complies with JEDEC standard JESD7A (2.0V to 6.0V)
• ESD protection (HBM JESD22-A114F exceeds 2000V, MM JESD22-A115-A exceeds 200V)
• Input leakage current is ±0.1μA maximum at (VI=VCC or GND;VCC = 5.5V, 25°C)
• Supply current is 4μA maximum at (VI=VCC or GND;IO = 0A;VCC = 5.5V, 25°C)
• Propagation delay is 20ns typical at (VCC = 4.5V)
• Operating temperature range from -40°C to +125°C, SO16 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.