74LVC573APW,118

74LVC573APW,118 is an 8bit D-type transparent latch with 3-state outputs. This device features latch enable (LE) and output enable (active-low OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on active-low OE causes the outputs to assume a high-impedance OFF-state. Operation of the active-low OE input does not affect the state of the latches. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of these devices as translators in mixed 3.3V and 5V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

• Wide supply voltage range from 1.65V to 3.6V
• Overvoltage tolerant inputs to 5.5V, CMOS low power consumption
• Direct interface with TTL levels, IOFF circuitry provides partial power-down mode operation
• High-impedance when VCC = 0V, flow-through pinout architecture
• Input leakage current is ±0.1μA typ at (VCC = 3.6V; VI=5.5V or GND, -40°C to +85°C)
• Supply current is 0.1μA typ at (VCC = 3.6V;VI=VCC or GND;IO = 0A, -40°C to +85°C)
• Input capacitance is 5pF typ at (VCC = 0V to 3.6V;VI=GND to VC, -40°C to +85°C)
• Propagation delay is 7.8ns typ at (VCC = 1.65V to 1.95V, -40°C to +85°C)
• Operating temperature range from -40°C to +125°C
• TSSOP20 package

Warnings

Market demand for this product has caused an extension in leadtimes. Delivery dates may fluctuate. Product exempt from discounts.